CMOS Logic Ultra Shallow Junction formation with high activation rate Source and Drain junction formation using low thermal budget, high surface temperature and diffusion less process.

Electromagnetic coupling of Laser light on CMOS structures (simulation).

Key Features:

• Low thermal budget melt and submelt process
• Nano-localization of the process at the surface
• Diffusion less activation
• Full defect annealing
• Si and Ge compatible
• Bulk or SOI substrates
• Gate stack and surface integrity using Anti Reflection Coating
• Compatible with main implant techniques : Beam Line, PLAD, Cluster