POWER DEVICES with less process steps and better performance Backside junction formation can now be done at end-of-line with no adverse impact on completed nMOS and pMOS devices on the front side,ILDs, Buffer and Barrier­ layers, Cu-interconnect…Rethink and shorten your process-flow to minimize processing and handling of thinned wafers.

Key features:

• Thin wafer handling and processing (Taiko® and non-Taiko®)
• Integrity of underlying layers and devices (Front Side at room temperature)
• Over 1µm deep backside junction activation
• High activation rate
• Junction profile engineering (single and multiple implants)
• APMC® Real time in-situ process control